as12 (v1.2) absolute assembler for the Motorola CPU12 Executed: Tue Mar 21 18:13:35 2000 ******************************************************************************* *REVISION HISTORY: * *DATE REV. NO. DESCRIPTION * *March 16, 2000 1.00 PCF8593 RTC and SPI EEPROM *Author: Exequiel Rarama ******************************************************************************* ; ; ---------------------------- ; ADAPT-912MX1 ; ---------------------------- ;REGS912A.INC is an external file containing the 68HC912 register definitions ; #include REGS912A.INC ;MC68HC912B32 REGISTER MAP ;MEMORY BLOCK BEGINS AT 0000H AND ENDS AT 00FFH 0000 REG EQU $0000 0000 PORTA EQU $0000 ;PORTA 0001 PORTB EQU $0001 ;PORTB 0002 DDRA EQU $0002 ;PORTA - DATA DIRECTION REGISTER 0003 DDRB EQU $0003 ;PORTB - DATA DIRECTION REGISTER 0008 PORTE EQU $0008 ;PORTE 0009 DDRE EQU $0009 ;PORTE - DATA DIRECTION REGISTER 000a PEAR EQU $000A ;PEAR - PORTE ASSIGNMENT REGISTER 000b MODE EQU $000B ;MODE - MODE REGISTER 000c PUCR EQU $000C ;PUCR - PULL UP CONTROL REGISTER 000d RDRIV EQU $000D ;RDRIV - REDUCED DRIVE OF I/O LINES 0010 ER 0011 ION REGISTER 0012 ON REGISTER 0013 MISC EQU $0013 ;MISC - MISCELLANEOUS MAPPING CONTROL REGISTER 0014 RTICTL EQU $0014 ;RTICTL - REAL TIME INTERRUPT CONTROL REGISTER 0015 RTIFLG EQU $0015 ;RTIFLG - REAL TIME INTERRUPT FLAG REGISTER 0016 COPCTL EQU $0016 ;COPCTL - COP CONTROL REGISTER 0017 COPRST EQU $0017 ;COPRST - ARM/RESET COP TIMER REGISTER 0018 ITST0 EQU $0018 ;ITST0 0019 ITST1 EQU $0019 ;ITST1 001a ITST2 EQU $001A ;ITST2 001b ITST3 EQU $001B ;ITST3 001e INTCR EQU $001E ;INTCR - INTERRUPT CONTROL REGISTER 001f HPRIO EQU $001F ;HPRIO - HIGHEST PRIORITY I INTERRRUPT 0020 BRKCT0 EQU $0020 ;BRKCT0 0021 BRKCT1 EQU $0021 ;BRKCT1 0022 BRKAH EQU $0022 ;BRKAH 0023 BRKAL EQU $0023 ;BRKAL 0024 BRKDH EQU $0024 ;BRKDH 0025 BRKDL EQU $0025 ;BRKDL 0040 PWCLK EQU $0040 ;PWCLK - 0041 PWPOL EQU $0041 ;PWPOL - 0042 PWEN EQU $0042 ;PWEN - 0043 PWPRES EQU $0043 ;PWPRES - 0044 PWSCAL0 EQU $0044 ;PWSCAL0 0045 PWSCNT0 EQU $0045 ;PWSCNT0 0046 PWSCAL1 EQU $0046 ;PWSCAL1 0047 PWSCNT1 EQU $0047 ;PWSCNT1 0048 PWCNT0 EQU $0048 ;PWCNT0 0049 PWCNT1 EQU $0049 ;PWCNT1 004a PWCNT2 EQU $004A ;PWCNT2 004b PWCNT3 EQU $004B ;PWCNT3 004c PWPER0 EQU $004C ;PWPER0 004d PWPER1 EQU $004D ;PWPER1 004e PWPER2 EQU $004E ;PWPER2 004f PWPER3 EQU $004F ;PWPER3 0050 PWDTY0 EQU $0050 ;PWDTY0 0051 PWDTY1 EQU $0051 ;PWDTY1 0052 PWDTY2 EQU $0052 ;PWDTY2 0053 PWDTY3 EQU $0053 ;PWDTY3 0054 PWCTL EQU $0054 ;PWCTL 0055 PWTST EQU $0055 ;PWTST 0056 PORTP EQU $0056 ;PORTP - PORTP REGISTER 0057 DDRP EQU $0057 ;DDRP - DATA DIRECTION REGISTER 0060 ATDCTL0 EQU $0060 ;ATDCTL0 - RESERVED 0061 ATDCTL1 EQU $0061 ;ATDCTL1 - RESERVED 0062 ATDCTL2 EQU $0062 ;ATDCTL2 - ATD CONTROL REGISTER 0063 ATDCTL3 EQU $0063 ;ATDCTL3 - ATD CONTROL REGISTER 0064 ATDCTL4 EQU $0064 ;ATDCTL4 - ATD CONTROL REGISTER 0065 ATDCTL5 EQU $0065 ;ATDCTL5 - ATD CONTROL REGISTER 0066 ATDSTAT EQU $0066 0066 ATDSTATH EQU $0066 ;ATDSTAT - ATD STATUS HIGH REGISTER 0067 ATDSTATL EQU $0067 ;ATDSTAT - LOW REGISTER 0068 STDTEST EQU $0068 0068 ATDTESTH EQU $0068 ;ATDTEST - ATD TEST HIGH REGISTER 0069 ATDTESTL EQU $0069 ;ATDTEST - LOW REGISTER 006f PORTAD EQU $006F ;PORTAD - PORT AD DATA INPUT REGISTER 0070 ADR0H EQU $0070 ;ADR0H 0072 ADR1H EQU $0072 ;ADR1H 0074 ADR2H EQU $0074 ;ADR2H 0076 ADR3H EQU $0076 ;ADR3H 0078 ADR4H EQU $0078 ;ADR4H 007a ADR5H EQU $007A ;ADR5H 007c ADR6H EQU $007C ;ADR6H 007e ADR7H EQU $007E ;ADR7H 0080 TIOS EQU $0080 ;TIOS - TIMER INPUT CAPTURE/OUTPUT COMPARE SELECU--I´—oÊ~o€,\,-l 0081 CFORC EQU $0081 ;CFORC - TIMER COMPARE FORCE REGISTER 0082 OC7M EQU $0082 ;OC7M - OUTPUT COMPARE 7 MASK REGISTER 0083 OC7D EQU $0083 ;OC7D - OUTPUT COMPARE 7 DATA REGISTER 0084 TCNT EQU $0084 0084 TCNTH EQU $0084 ;TCNT - TIMER COUNT HIGH REGISTER 0085 TCNTL EQU $0085 ;TCNT - HIGH REGISTER 0086 TSCR EQU $0086 ;TSCR - TIMER SYSTEM CONTROL REGISTER 0087 TQCR EQU $0087 ;TQCR - RESERVED 0088 TCTL1 EQU $0088 ;TCTL1 - TIMER CONTROL REGISTER 1 0089 TCTL2 EQU $0089 ;TCTL2 - TIMER CONTROL REGISTER 2 008a TCTL3 EQU $008A ;TCTL3 - TIMER CONTROL REGISTER 3 008b TCTL4 EQU $008B ;TCTL4 - TIMER CONTROL REGISTER 4 008c TMSK1 EQU $008C ;TMSK1 - TIMER INTERRUPT MASK 1 008d TMSK2 EQU $008D ;TMSK2 - TIMER INTERRUPT MASK 2 008e TFLG1 EQU $008E ;TFLG1 - TIMER INTERRUPT FLAG 1 008f TFLG2 EQU $008F ;TFLG2 - TIMER INTERRUPT FLAG2 0090 TC0 EQU $0090 0090 TC0H EQU $0090 ;TC0 - TIMER INPUT/CAPTURE COMPARE HIGH REGISTER1--I´—oÊ~o€,\,-l 0091 TC0L EQU $0091 ;TC0 - LOW REGISTER 0092 TC1 EQU $0092 0092 TC1H EQU $0092 ;TC1 - HIGH REGISTER 0093 TC1L EQU $0093 ;TC1 - LOW REGISTER 0094 TC2 EQU $0094 0094 TC2H EQU $0094 ;TC2 - HIGH REGISTER 0095 TC2L EQU $0095 ;TC2 - LOW REGISTER 0096 TC3 EQU $0096 0096 TC3H EQU $0096 ;TC3 - HIGH REGISTER 0097 TC3L EQU $0097 ;TC3 - LOW REGISTER 0098 TC4 EQU $0098 0098 TC4H EQU $0098 ;TC4 - HIGH REGISTER 0099 TC4L EQU $0099 ;TC4 - LOW REGISTER 009a TC5 EQU $009A 009a TC5H EQU $009A ;TC5 - HIGH REGISTER 009b TC5L EQU $009B ;TC5 - LOW REGISTER 009c TC6 EQU $009C 009c TC6H EQU $009C ;TC6 - HIGH REGISTER 009d TC6L EQU $009D ;TC6 - LOW REGISTER 009e TC7 EQU $009E 009e TC7H EQU $009E ;TC7 - HIGH REGISTER 009f TC7L EQU $009F ;TC7 - LOW REGISTER 00a0 PACTL EQU $00A0 ;PATCL - PULSE ACCUMULATOR CONTROL REGISTER 00a1 PAFLG EQU $00A1 ;PAFLG - PULSE ACCUMULATOR FLAG REGISTER 00a2 PACNT EQU $00A2 00a2 PACNTH EQU $00A2 ;PACNT - 16 BIT PULSE ACCUMULATOR COUNT HIGH REGN1-I´—oÊ~o€,\,-l 00a3 PACNTL EQU $00A3 ;PACNT - LOW REGISTER 00ad TIMTST EQU $00AD ;TIMTST - TIMER TEST REGISTER 00ae PORTT EQU $00AE ;PORTT 00af DDRT EQU $00AF ;PORTT - DATA DIRECTION REGISTER 00c0 SC0BDH EQU $00C0 ;SC0BDH - SCI BAUD RATE CONTROL REGISTER 00c1 SC0BDL EQU $00C1 ;SC0BDL - SCI BAUD RATE CONTROL REGISTER 00c2 SC0CR1 EQU $00C2 ;SC0CR1 - SCI CONTROL REGISTER 00c3 SC0CR2 EQU $00C3 ;SC0CR2 - SCI CONTROL REGISTER 00c4 SC0SR1 EQU $00C4 ;SC0SR1 - SCI STATUS REGISTER 00c5 SC0SR2 EQU $00C5 ;SC0SR2 - SCI STATUS REGISTER 00c6 SC0DRH EQU $00C6 ;SC0DRH - SCI DATA REGISTER 00c7 SC0DRL EQU $00C7 ;SC0DRL - SCI DATA REGISTER 00d0 SP0CR1 EQU $00D0 ;SP0CR1 - SPI CONTROL REGISTER 00d1 SP0CR2 EQU $00D1 ;SP0CR2 - SPI CONTROL REGISTER 00d2 SP0BR EQU $00D2 ;SP0BR - SPI BAUD RATE REGISTER 00d3 SP0SR EQU $00D3 ;SP0SR - SPI STATUS REGISTER 00d5 SP0DR EQU $00D5 ;SP0DR - SPI DATA REGISTER 00d6 PORTS EQU $00D6 ;PORTS 00d7 DDRS EQU $00D7 ;PORTS - DATA DIRECTION REGISTER 00db PURDS EQU $00DB ;PURDS - 00f0 EEMCR EQU $00F0 ;EEMCR - EEPROM MODULE CONFIGURATION 00f1 EEPROT EQU $00F1 ;EEPROT - EEPROM BLOCK PROTECT 00f2 EETST EQU $00F2 ;EETST - EEPROM TEST 00f3 EEPROG EQU $00F3 ;EEPROG - EEPROM CONTROL 00f4 FEELCK EQU $00F4 ;FEELCK - 00f5 FEEMCR EQU $00F5 ;FEEMCR - 00f6 FEETST EQU $00F6 ;FEETST - 00f7 FEECTL EQU $00F7 ;FEECTL - 00f8 BCR1 EQU $00F8 ;BCR1 - 00f9 BSVR EQU $00F9 ;BSVR - 00fa BCR2 EQU $00FA ;BCR2 - 00fb BDR EQU $00FB ;BDR - 00fc BARD EQU $00FC ;BARD - 00fd DLCSCR EQU $00FD ;DLCSCR - 00fe PORTDLC EQU $00FE ;PORTDLC 00ff DDRDLC EQU $00FF ;DDRDLC - DATA DIRECTION REGISTER FOR PORT DLC * Operational Parameters 0019 _100MS equ 25 003d _250MS equ 61 007d _500MS equ 125 00fa _1SECOND equ 250 01f4 _2SECONDS equ 500 02ee _3SECONDS equ 750 04e2 _5SECONDS equ 1250 09c4 _10SECONDS equ 2500 186a _25SECONDS equ 6250 0800 RAM equ $0800 ;68HC912B32 internal RAM 0bff STACK equ $0bff ;Stack at top of internal ram * Operational Constants 00ff true equ $ff 0000 false equ $00 000d CR equ $D 000a LF equ $A 0020 SPACE equ $20 * Masks ;SCI Variables 002c scimask equ %00101100 ;RIE - SCI Interrupt enable ;RE - Receiver Enable 0020 RDRFflag equ %00100000 ;RDRF - Receive Data Register Full flag 0080 TDREflag equ %10000000 ;TDRE - Transmit Data Register Empty flag ;Baud rate definitions ;MCLK=8MHz 11c1 BAUD110 equ 4545 ;(baud) 110 baud with 16 Mhz crystal 0683 BAUD300 equ 1667 ;(baud) 300 baud with 16 Mhz crystal 0341 BAUD600 equ 833 ;(baud) 600 baud with 16 Mhz crystal 01a1 BAUD1200 equ 417 ;(baud) 1200 baud with 16 Mhz crystal 00d0 BAUD2400 equ 208 ;(baud) 2400 baud with 16 Mhz crystal 0068 BAUD4800 equ 104 ;(baud) 4800 baud with 16 Mhz crystal 0034 BAUD9600 equ 52 ;(baud) 9600 baud with 16 Mhz crystal 0023 BAUD14400 equ 35 ;(baud) 14400 baud with 16 Mhz crystal 001a BAUD19200 equ 26 ;(baud) 19200 baud with 16 Mhz crystal 000d BAUD38400 equ 13 ;(baud) 38400 baud with 16 Mhz crystal *----------------------------------------------------------------------------- ;Spi initialization variables 0050 spi_mask1 equ %01010000 ;SPE,MSTR=1, SWOM,CPOL,CPHA=0 00e0 spi_mask2 equ %11100000 ;Bit 7,6,5=1 the rest=0 0054 spi_mask3 equ %01010100 ;SPE,MSTR=1, SWOM,CPOL=0, CPHA=1 0000 spi_baud1 equ %00000000 ;4.0 Mhz 0001 spi_baud2 equ %00000001 ;2.0 Mhz 0002 spi_baud3 equ %00000010 ;1.0 Mhz 0003 spi_baud4 equ %00000011 ;0.5 Mhz 0004 spi_baud5 equ %00000100 ;250 kHz 0005 spi_baud6 equ %00000101 ;125 kHz 0006 spi_baud7 equ %00000110 ;62.5 kHz 0007 spi_baud8 equ %00000111 ;31.3 kHz 0080 SPIF equ %10000000 ;flag after the 8th clock 0080 SPIE equ %10000000 ;Spi interrupt enable 0001 LSBF equ %00000001 ;SPI LSB First enable 0010 slave_select equ $10 ;spi slave select ;Delay 0010 us8 equ 16 ;2 microsecond delay 0008 us1 equ 8 ;1 microsecond delay 0080 TEN equ $80 *----------------------------------------------------------------------------- 0800 org RAM * System Variables 0800 TEMP1 ds 1 0801 TEMP2 ds 1 0802 H ds 1 ;used in binary to decimal conversion 0803 TO ds 1 ;------------- ;RTC Variables ;------------- 0804 spi_read ds 1 0805 spi_write ds 1 0806 rtc_reg_address ds 1 0807 read_write_flag ad 0808 ack_flag ds 1 ;acknowledged flag 0809 time_flag ds 1 080a date_flag ds 1 time_temp 080b time_seconds_hundred ds 1 080c time_seconds ds 1 080d time_minutes ds 1 080e time_hours ds 1 080f time_days ds 1 0810 time_months ds 1 0811 leap_var ds 1 0812 DBUFR ds 5 0817 result ds 4 081b operand ds 2 081d u_delay_var ds 2 081f spi_int_flag ds 1 ;spi eeprom variables 0820 eeprom_data ds 1 ;spi eeprom data buffer 0821 eeprom_address ds 2 ;spi eeprom address 0823 sci_flag ds 1 ;Valid sci value 0824 char_counter ds 1 0825 ee_rd_wr_flag ds 1 ;routine address 0826 states ds 2 1000 org $1000 1000 time_years ds 2 ;the year is saved in battery-backed RAM 1002 leap_year ds 1 ***************************** Program ******************************* 2000 org $2000 RESET 2000 14 10 sei Init: ;This is where the RESET vector points to ;Initialize Stack 2002 cf 0b ff lds #STACK ;initialize stack pointer ;Initialize COP 2005 79 00 16 clr COPCTL ;turn COP off ;Initialize Serial Communication Interface 2008 18 0b 0c 00 c3 movb #$0c,SC0CR2 ;enable SCI 0 rx & tx 200d 18 0b 00 00 c2 movb #0,SC0CR1 ; for polled operation 2012 18 03 00 34 00 c0 movw #BAUD9600,SC0BDH ;Set baud rate 2018 79 08 23 clr sci_flag ;Initialize flag 201b 16 23 2e jsr RTC_INIT ;initialize the real-time clock/calendar chip 201e 16 20 71 jsr ShowMenu ;display menu in terminal window 2021 10 ef cli 2023 16 28 f6 jsr init_spi 2026 16 20 38 jsr go_power ;Initialize states ;----------------------------------------------------------------------------- ;Main loop - all routine are process here ; main 2029 b6 08 25 ldaa ee_rd_wr_flag 202c 26 03 bne main10 202e 16 20 a8 jsr ProcessCommand ;check for user command main10 2031 fe 08 26 ldx states ;process states 2034 15 00 jsr 0,x 2036 20 f1 bra main ;----------------------------------------------------------------------------- go_power 2038 ce 20 3f ldx #wait_here 203b 7e 08 26 stx states 203e 3d rts wait_here 203f 1f 08 25 01 13 brclr ee_rd_wr_flag,%01,wait_here10 2044 ce 29 36 ldx #go_read 2047 7e 08 26 stx states 204a 18 0b 04 08 24 movb #4,char_counter ;initialize counter 204f 18 03 00 00 08 21 movw #0,eeprom_address ;Initialize address 2055 20 19 bra wait_here20 wait_here10 2057 1f 08 25 02 14 brclr ee_rd_wr_flag,%10,wait_here20 205c ce 29 6f ldx #go_write 205f 7e 08 26 stx states 2062 18 0b 06 08 24 movb #6,char_counter ;initialize counter 2067 18 03 00 00 08 21 movw #0,eeprom_address ;Initialize address 206d 79 08 20 clr eeprom_data wait_here20 2070 3d rts *********************************************************************** *Procedure Definitions: *********************************************************************** ShowMenu: 2071 16 21 b5 jsr PutDblLine 2074 ce 22 b8 ldx #M_HEADER1 2077 16 21 c5 jsr SendString 207a 16 21 aa jsr PutNewLine 207d ce 21 d2 ldx #M_TIME 2080 16 21 c5 jsr SendString 2083 16 21 aa jsr PutNewLine 2086 ce 21 fc ldx #M_DATE 2089 16 21 c5 jsr SendString 208c 16 21 aa jsr PutNewLine 208f ce 22 17 ldx #M_READ 2092 16 21 c5 jsr SendString 2095 16 21 aa jsr PutNewLine 2098 ce 22 5f ldx #M_WRITE 209b 16 21 c5 jsr SendString 209e 16 21 aa jsr PutNewLine 20a1 ce 22 b6 ldx #M_PROMPT 20a4 16 21 c5 jsr SendString 20a7 3d rts ProcessCommand: 20a8 16 21 16 jsr GetChar 20ab f6 08 23 ldab sci_flag ;check for character 20ae 27 43 beq PCX 20b0 79 08 23 clr sci_flag ;check for character 20b3 16 21 a3 jsr SendByte ;echo the character 20b6 8a 20 oraa #$20 ;convert to lower case, if required 20b8 81 74 cmpa #'t' ;read/set time 20ba 18 27 00 17 lbeq PCT 20be 81 64 cmpa #'d' ;read/set date 20c0 18 27 00 19 lbeq PCD 20c4 81 72 cmpa #'r' ;Read spi 20c6 18 27 00 1b lbeq PCR 20ca 81 77 cmpa #'w' ;Write spi 20cc 18 27 00 1c lbeq PCW 20d0 16 20 71 jsr ShowMenu ;display menu in terminal window 20d3 20 1e bra PCX ; and exit PCT: 20d5 16 21 aa jsr PutNewLine 20d8 16 23 e8 jsr GET_TIME 20db 20 16 bra PCX PCD: 20dd 16 21 aa jsr PutNewLine 20e0 16 24 dc jsr GET_DATE 20e3 20 0e bra PCX PCR: ; jsr PutNewLine 20e5 18 0b 01 08 25 movb #%01,ee_rd_wr_flag 20ea 20 07 bra PCX PCW: ; jsr PutNewLine 20ec 18 0b 02 08 25 movb #%10,ee_rd_wr_flag 20f1 20 00 bra PCX PCX 20f3 3d rts HexByte2Dec ;Supply hex value to be converted in B register 20f4 87 clra ;numerator in D, denominator in X 20f5 ce 00 64 ldx #100 ;remainder in D, quotient in X 20f8 18 10 idiv ;B is lo-order byte 20fa b7 c5 xgdx 20fc 7b 08 02 stab H ;8 bit quotient in B 20ff b7 c5 xgdx 2101 ce 00 0a ldx #10 ;H=0X TO=packed BCD 2104 18 10 idiv 2106 7b 08 03 stab TO 2109 b7 c5 xgdx 210b 58 aslb 210c 58 aslb 210d 58 aslb 210e 58 aslb 210f fa 08 03 orab TO 2112 7b 08 03 stab TO 2115 3d rts GetChar: * Fetches one character from SCI0, * and returns it in register A. GC1: 2116 96 c4 ldaa SC0SR1 ;get sci flags 2118 84 20 anda #RDRFflag ;mask off irrelevant bits 211a 27 09 beq GC2 ;loop until character found 211c 96 c7 ldaa SC0DRL ;get character 211e 18 0b 01 08 23 movb #1,sci_flag 2123 20 03 bra GC3 GC2 2125 79 08 23 clr sci_flag GC3 2128 3d rts get_time_char 2129 96 c4 ldaa SC0SR1 ;get sci flags 212b 84 20 anda #RDRFflag ;mask off irrelevant bits 212d 27 fa beq get_time_char ;loop until character found 212f 96 c7 ldaa SC0DRL ;get character 2131 3d rts GetByte: * Converts 2 hex characters to a single byte value, * and returns it in register A. GB1: 2132 16 21 16 jsr GetChar 2135 16 21 49 jsr Hex2Bin 2138 48 lsla 2139 48 lsla 213a 48 lsla 213b 48 lsla 213c 7a 08 00 staa TEMP1 213f 16 21 16 jsr GetChar 2142 16 21 49 jsr Hex2Bin 2145 ba 08 00 oraa TEMP1 2148 3d rts Hex2Bin: * Converts an ASCII hex character in register A * to a binary nibble and returns it in register A. 2149 81 39 cmpa #'9 214b 23 02 bls HEX 214d 8b 09 adda #9 214f 84 0f HEX: anda #$f 2151 3d rts GetAddress: * Extracts load address and returns it in register Y. 2152 37 pshb ;preserve byte count 2153 16 21 32 jsr GetByte 2156 7a 08 01 staa TEMP2 2159 16 21 32 jsr GetByte 215c 18 0e tab 215e b6 08 01 ldaa TEMP2 2161 b7 c6 xgdy 2163 33 pulb 2164 3d rts SendDecByte * value is in B 2165 87 clra 2166 16 20 f4 jsr HexByte2Dec 2169 b6 08 02 ldaa H 216c 8b 30 adda #'0' 216e 16 21 a3 jsr SendByte 2171 b6 08 03 ldaa TO 2174 16 21 78 jsr SendASCIIHex 2177 3d rts SendASCIIHex * value in A 2178 36 psha 2179 84 f0 anda #$F0 217b 44 lsra 217c 44 lsra 217d 44 lsra 217e 44 lsra 217f 81 0a cmpa #$A 2181 2d 06 blt SAH1 2183 80 0a suba #$A 2185 8b 41 adda #'A' 2187 20 02 bra SAH2 SAH1 2189 8b 30 adda #'0' SAH2 218b 16 21 a3 jsr SendByte 218e 32 pula 218f 36 psha 2190 84 0f anda #$0F 2192 81 0a cmpa #$A 2194 2d 06 blt SAH3 2196 80 0a suba #$A 2198 8b 41 adda #'A' 219a 20 02 bra SAH4 SAH3 219c 8b 30 adda #'0' SAH4 219e 16 21 a3 jsr SendByte 21a1 32 pula 21a2 3d rts SendByte: * Transmits a byte, contained in register A, to the serial device via the SCI. SB1 21a3 d6 c4 ldab SC0SR1 ;wait for transmit data register empty (TDRE) 21a5 2a fc bpl SB1 21a7 5a c7 staa SC0DRL ;send byte 21a9 3d rts PutNewLine 21aa 86 0d ldaa #CR 21ac 16 21 a3 jsr SendByte 21af 86 0a ldaa #LF 21b1 16 21 a3 jsr SendByte 21b4 3d rts PutDblLine 21b5 86 0d ldaa #CR 21b7 16 21 a3 jsr SendByte 21ba 86 0a ldaa #LF 21bc 16 21 a3 jsr SendByte 21bf 86 0a ldaa #LF 21c1 16 21 a3 jsr SendByte 21c4 3d rts SendString: * x contains starting address of string RV1 21c5 a6 00 ldaa 0,X ;$FF denotes end of string 21c7 81 ff cmpa #$ff 21c9 27 06 beq RVX 21cb 16 21 a3 jsr SendByte 21ce 08 inx 21cf 20 f4 bra RV1 RVX 21d1 3d rts ******************************************************************************* * Messages ******************************************************************************* * Messages 21d2 54 20 3d 3e 20 53 M_TIME fcc 'T => Set Time (hh:mm:ss) [24-hour format]' 65 74 20 54 69 6d 65 20 28 68 68 3a 6d 6d 3a 73 73 29 20 5b 32 34 2d 68 6f 75 72 20 66 6f 72 6d 61 74 5d 21fb ff fcb $ff 21fc 44 20 3d 3e 20 53 M_DATE fcc 'D => Set Date (yyyy/mm/dd)' 65 74 20 44 61 74 65 20 28 79 79 79 79 2f 6d 6d 2f 64 64 29 2216 ff fcb $ff 2217 52 20 3d 3e 20 52 M_READ fcc 'R => Read spi EEPROM (Any address in hex)' 65 61 64 20 73 70 69 20 45 45 50 52 4f 4d 20 28 41 6e 79 20 61 64 64 72 65 73 73 20 69 6e 20 68 65 78 29 2240 0d 0a fcb CR,LF 2242 65 67 2e 20 52 58 fcc 'eg. RXXXX where XXXX=address' 58 58 58 20 77 68 65 72 65 20 58 58 58 58 3d 61 64 64 72 65 73 73 225e ff fcb $ff 225f 57 20 3d 3e 20 57 M_WRITE fcc 'W => Write to spi EEPROM (Any address in hex)' 72 69 74 65 20 74 6f 20 73 70 69 20 45 45 50 52 4f 4d 20 28 41 6e 79 20 61 64 64 72 65 73 73 20 69 6e 20 68 65 78 29 228c 0d 0a fcb CR,LF 228e 65 67 2e 20 57 58 fcc 'eg. WXXXXYY where XXXX=address, YY=data' 58 58 58 59 59 20 77 68 65 72 65 20 58 58 58 58 3d 61 64 64 72 65 73 73 2c 20 59 59 3d 64 61 74 61 22b5 ff fcb $ff 22b6 3f M_PROMPT fcc '?' 22b7 ff fcb $ff 22b8 20 41 44 41 50 54 M_HEADER1 fcc ' ADAPT912 MX1 SPI EEPROM/RTC UTILITY VERSION 1.00' 39 31 32 20 4d 58 31 20 53 50 49 20 45 45 50 52 4f 4d 2f 52 54 43 20 55 54 49 4c 49 54 59 20 56 45 52 53 49 4f 4e 20 31 2e 30 30 22e9 ff fcb $ff 22ea 43 75 72 72 65 6e M_CURRENT_TIME fcc 'Current Time: ' 74 20 54 69 6d 65 3a 20 22f8 ff fcb $ff 22f9 4e 65 77 20 54 69 M_NEW_TIME fcc 'New Time: ' 6d 65 3a 20 2303 ff fcb $ff 2304 43 75 72 72 65 6e M_CURRENT_DATE fcc 'Current Date: ' 74 20 44 61 74 65 3a 20 2312 ff fcb $ff 2313 4e 65 77 20 44 61 M_NEW_DATE fcc 'New Date: ' 74 65 3a 20 231d ff fcb $ff 231e 4e 6f 74 20 69 6d M_NOT fcc 'Not implemented' 70 6c 65 6d 65 6e 74 65 64 232d ff fcb $ff ; ;----------------------------------------------------------------------------- ;The "include" sub-routines are external, and are linked during assembly. #include RTC.ASM ;rtc.asm ******************************************************************************* *REVISION HISTORY: * *DATE REV. NO. DESCRIPTION * *Oct 29, 1999 1.00 RTC clean up *Author: Exequiel Rarama ******************************************************************************* ; ; ---------------------------- ; ADAPT-912MX1 Flash Utilities ; ---------------------------- ; --------------------------- ; Clock RTC - RTC Routines ; --------------------------- ;clock modes 0083 status1 equ %10000011 ;clock control/status register 0003 status2 equ %00000011 ;clock control/status register 000b status3 equ %00001011 ;clock control/status register ; read date and month directly. 0000 rtc_control_reg_address equ 0 0001 millisecond_reg_address equ 1 0002 seconds_reg_address equ 2 0003 minutes_reg_address equ 3 0004 hours_reg_address equ 4 0005 year_date_reg_address equ 5 0006 week_month_reg_address equ 6 0007 timer_reg_address equ 7 0008 alarm_cntrl_reg_address equ 8 00a3 rtc_read_address equ %10100011 ;address of rtc clock 00a2 rtc_write_address equ %10100010 ;address of rtc clock 0080 SDA EQU %10000000 ;SERIAL DATA 0040 SCL EQU %01000000 ;SERIAL CLOCK FOR THE DATA ; ;Required Rams variables ;------------- ;RTC Variables ;------------- ;spi_read ds 1 ;spi_write ds 1 ;rtc_reg_address ds 1 ;read_write_flag ds ead ;ack_flag ds 1 ;acknowledged flag ;time variables ;time_temp ;time_seconds_hundred ds 1 ;time_seconds ds 1 ;time_minutes ds 1 ;time_hours ds 1 ;time_days ds 1 ;time_months ds 1 ;leap_year ds 1 ;time_years ds 1 ;time_flag ds 1 ;date_flag ds 1 ; ;----------------------------------------------------------------------------- ; RTC_INIT 232e 79 08 09 clr time_flag ;clear flags for sci parsing 2331 79 08 0a clr date_flag 2334 3d rts 2335 79 08 0b clr time_seconds_hundred 2338 79 08 0c clr time_seconds 233b 79 08 0d clr time_minutes 233e 79 08 0e clr time_hours ; ;Initialize month and date to January 1 2341 18 0b 01 08 10 movb #%00000001,time_months ;January 2346 18 0b 01 08 0f movb #%00000001,time_days ;1st ; movb #%00010001,time_days ;eg. shows 11th as the date. 234b 18 0b 98 10 00 movb #%10011000,time_years ;98 and in this case the year 1998 2350 20 0e bra TIME_INIT ; NEW_TIME_INIT 2352 79 08 0b clr time_seconds_hundred 2355 20 09 bra TIME_INIT NEW_DATE_INIT 2357 16 26 65 jsr READ_TIME_HR 235a 16 26 53 jsr READ_TIME_MIN 235d 16 26 41 jsr READ_TIME_SEC ; TIME_INIT 2360 18 0b a2 08 05 movb #rtc_write_address,spi_write ;slave address 2365 18 0b 00 08 06 movb #rtc_control_reg_address,rtc_reg_address ;slave control register 236a 16 27 39 jsr WRITE_MOD ; ;status 236d c6 08 ldab #8 236f 86 83 ldaa #status1 ;dump status data into rtc 2371 16 27 78 jsr clock_bits 2374 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc ; ;------------------------------- ;Time are set to 00:00:00:00 in 24h format ;Date are set to Jan 1 and the year to 1. The actual year value (ie 1998) must ; set somewhere else. ; ;hundredths of a second 2377 c6 08 ldab #8 ;the rtc is auto incremented 2379 b6 08 0b ldaa time_seconds_hundred ;address 1 237c 16 27 78 jsr clock_bits 237f 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc ;seconds 2382 c6 08 ldab #8 ;the rtc is auto incremented 2384 b6 08 0c ldaa time_seconds ;address 2 2387 16 27 78 jsr clock_bits 238a 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc ;minutes 238d c6 08 ldab #8 ;the rtc is auto incremented 238f b6 08 0d ldaa time_minutes ;address 3 2392 16 27 78 jsr clock_bits 2395 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc ;hours 2398 c6 08 ldab #8 ;the rtc is auto incremented 239a b6 08 0e ldaa time_hours ;address 4 239d 16 27 78 jsr clock_bits 23a0 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc 23a3 b6 08 09 ldaa time_flag 23a6 26 16 bne time_upx ;year/date 23a8 c6 08 ldab #8 ;the rtc is auto incremented 23aa b6 08 0f ldaa time_days ;address 5 - set date to 1st 23ad 16 27 78 jsr clock_bits ; and year to 1 23b0 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc ;weekday/month 23b3 c6 08 ldab #8 ;the rtc is auto incremented 23b5 b6 08 10 ldaa time_months ;address 6 - set month to 1st 23b8 16 27 78 jsr clock_bits ; and weekday 0 23bb 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc time_upx 23be 16 27 b8 jsr stop_condition ; 23c1 16 27 fd jsr small_delay ; ;Update to new time and Initialize clock to start counting ; time_update 23c4 79 08 07 clr read_write_flag 23c7 18 0b a2 08 05 movb #rtc_write_address,spi_write ;slave address 23cc 18 0b 00 08 06 movb #rtc_control_reg_address,rtc_reg_address ;slave control register 23d1 16 27 39 jsr WRITE_MOD ;status 23d4 c6 08 ldab #8 23d6 86 03 ldaa #status2 ;dump status data into rtc 23d8 16 27 78 jsr clock_bits 23db 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc 23de 16 27 b8 jsr stop_condition ; 23e1 79 08 09 clr time_flag 23e4 79 08 0a clr date_flag 23e7 3d rts ;----------------------------------------------------------------------------- GET_TIME 23e8 ce 22 ea ldx #M_CURRENT_TIME ;Send message 23eb 16 21 c5 jsr SendString 23ee 16 26 65 jsr READ_TIME_HR 23f1 b6 08 0e ldaa time_hours 23f4 16 24 c7 jsr display_time 23f7 86 3a ldaa #':' 23f9 16 21 a3 jsr SendByte 23fc 16 26 53 jsr READ_TIME_MIN 23ff b6 08 0d ldaa time_minutes 2402 16 24 c7 jsr display_time 2405 86 3a ldaa #':' 2407 16 21 a3 jsr SendByte 240a 16 26 41 jsr READ_TIME_SEC 240d b6 08 0c ldaa time_seconds 2410 16 24 c7 jsr display_time 2413 16 21 aa jsr PutNewLine 2416 ce 22 f9 ldx #M_NEW_TIME ;Send message 2419 16 21 c5 jsr SendString ; ;----------------------- ;get hour, minunte and second ; 241c 72 08 09 inc time_flag ;set flag to sci parsing 241f 79 08 0a clr date_flag ;get hour 2422 16 21 29 jsr get_time_char 2425 81 0d cmpa #CR ;cr 2427 27 62 beq time_ex 2429 81 30 cmpa #$30 242b 25 bb blo GET_TIME 242d 81 32 cmpa #$32 242f 22 b7 bhi GET_TIME 2431 16 21 a3 jsr SB1 ;Outchar before stripping 2434 80 30 suba #$30 ; 2436 16 24 bd jsr shift_a 2439 16 21 29 jsr get_time_char 243c 81 30 cmpa #$30 243e 25 a8 blo GET_TIME 2440 36 psha 2441 b6 08 00 ldaa TEMP1 2444 81 20 cmpa #$20 ;if first digit is 2 then 2446 26 05 bne NAN1 ; valid second digit range is 0 - 3 2448 32 pula 2449 81 33 cmpa #$33 244b 20 03 bra NAN2 NAN1: 244d 32 pula 244e 81 39 cmpa #$39 ;else valid range is 0 - 9 NAN2: 2450 22 96 bhi GET_TIME 2452 16 21 a3 jsr SB1 ;Outchar before stripping 2455 84 0f anda #%00001111 2457 f6 08 00 ldab TEMP1 245a 18 06 aba 245c 7a 08 0e staa time_hours 245f 86 3a ldaa #':' 2461 16 21 a3 jsr SendByte ;get minutes 2464 16 21 29 jsr get_time_char 2467 81 0d cmpa #CR ;cr 2469 27 18 beq time_hr_ex 246b 16 24 8f jsr get_minutes_second 246e 7a 08 0d staa time_minutes 2471 86 3a ldaa #':' 2473 16 21 a3 jsr SendByte ;get seconds 2476 16 21 29 jsr get_time_char 2479 81 0d cmpa #CR ;cr 247b 27 08 beq time_min_ex 247d 16 24 8f jsr get_minutes_second 2480 7a 08 0c staa time_seconds time_hr_ex 2483 20 02 bra timex time_min_ex 2485 20 00 bra timex timex 2487 18 20 fe c7 lbra NEW_TIME_INIT time_ex 248b 79 08 09 clr time_flag 248e 3d rts ; get_minutes_second 248f 81 30 cmpa #$30 2491 18 25 ff 53 lblo GET_TIME 2495 81 35 cmpa #$35 2497 18 22 ff 4d lbhi GET_TIME 249b 16 21 a3 jsr SB1 ;Outchar before stripping 249e 80 30 suba #$30 24a0 16 24 bd jsr shift_a 24a3 16 21 29 jsr get_time_char 24a6 81 30 cmpa #$30 24a8 18 25 ff 3c lblo GET_TIME 24ac 81 39 cmpa #$39 24ae 18 22 ff 36 lbhi GET_TIME 24b2 16 21 a3 jsr SB1 ;Outchar before stripping 24b5 84 0f anda #%00001111 24b7 f6 08 00 ldab TEMP1 24ba 18 06 aba 24bc 3d rts shift_a 24bd 84 0f anda #%00001111 24bf 48 asla ;Shift content 4 times 24c0 48 asla 24c1 48 asla 24c2 48 asla 24c3 7a 08 00 staa TEMP1 24c6 3d rts display_time 24c7 36 psha 24c8 47 asra ;Shift contents 4 times to carry 24c9 47 asra 24ca 47 asra 24cb 47 asra 24cc 84 0f anda #%00001111 24ce 8b 30 adda #$30 24d0 16 21 a3 jsr SB1 ;Outchar 24d3 32 pula 24d4 84 0f anda #%00001111 24d6 8b 30 adda #$30 24d8 16 21 a3 jsr SB1 24db 3d rts ;----------------------------------------------------------------------------- GET_DATE 24dc ce 23 04 ldx #M_CURRENT_DATE ;Send message 24df 16 21 c5 jsr SendString 24e2 ce 10 00 ldx #time_years 24e5 16 28 68 jsr HTOD ; ldaa 0,x ;display first 2 digit ; bsr display_time ; ldaa 1,x ;display last 2 digit ; bsr display_time 24e8 86 2f ldaa #'/' 24ea 16 21 a3 jsr SendByte 24ed 16 26 b7 jsr READ_TIME_MNTH 24f0 b6 08 10 ldaa time_months 24f3 07 d2 bsr display_time 24f5 86 2f ldaa #'/' 24f7 16 21 a3 jsr SendByte 24fa 16 26 77 jsr READ_TIME_DATE 24fd b6 08 0f ldaa time_days 2500 07 c5 bsr display_time 2502 16 21 aa jsr PutNewLine 2505 ce 23 13 ldx #M_NEW_DATE ;Send message 2508 16 21 c5 jsr SendString ; ;----------------------- ;get year, month and day ; 250b 79 08 09 clr time_flag ;set flag to sci parsing 250e 72 08 0a inc date_flag ;get the first 2 digit of the year 2511 ce 10 00 ldx #time_years 2514 16 21 29 jsr get_time_char 2517 81 0d cmpa #CR ;cr 2519 18 27 01 1d lbeq date_ex 251d 81 30 cmpa #$30 251f 25 bb blo GET_DATE 2521 81 39 cmpa #$39 2523 22 b7 bhi GET_DATE 2525 16 21 a3 jsr SB1 ;Outchar before stripping 2528 80 30 suba #$30 ; 252a 16 24 bd jsr shift_a 252d 16 21 29 jsr get_time_char 2530 81 30 cmpa #$30 2532 25 a8 blo GET_DATE 2534 81 39 cmpa #$39 2536 22 a4 bhi GET_DATE 2538 16 21 a3 jsr SB1 ;Outchar before stripping 253b 84 0f anda #%00001111 253d f6 08 00 ldab TEMP1 2540 18 06 aba 2542 6a 00 staa 0,x ;time_years ;get the last 2 digit of the year; 2544 16 21 29 jsr get_time_char 2547 81 0d cmpa #CR ;check if cr 2549 18 27 00 ed lbeq date_ex ;yes, then exit, not a complete date 254d 81 30 cmpa #$30 254f 25 8b blo GET_DATE 2551 81 39 cmpa #$39 2553 18 22 ff 85 lbhi GET_DATE 2557 16 21 a3 jsr SB1 ;Outchar before stripping 255a 80 30 suba #$30 ; 255c 16 24 bd jsr shift_a 255f 16 21 29 jsr get_time_char 2562 81 30 cmpa #$30 2564 18 25 ff 74 lblo GET_DATE 2568 81 39 cmpa #$39 256a 18 22 ff 6e lbhi GET_DATE 256e 16 21 a3 jsr SB1 ;Outchar before stripping 2571 84 0f anda #%00001111 2573 f6 08 00 ldab TEMP1 2576 18 06 aba 2578 6a 01 staa 1,x ;time_years 257a 86 2f ldaa #'/' 257c 16 21 a3 jsr SendByte ;calculate for leap year condition 257f 16 28 0e jsr bcd_to_hex 2582 7c 10 00 std time_years 2585 c4 03 andb #%00000011 ;check last 2 nibbles 2587 58 aslb 2588 58 aslb 2589 58 aslb 258a 58 aslb 258b 58 aslb 258c 58 aslb 258d 7b 08 11 stab leap_var ;get months 2590 16 21 29 jsr get_time_char 2593 81 0d cmpa #CR ;check if cr 2595 18 27 00 95 lbeq datex ;yes, go set date 2599 81 30 cmpa #$30 259b 18 25 ff 3d lblo GET_DATE 259f 81 31 cmpa #$31 25a1 18 22 ff 37 lbhi GET_DATE 25a5 16 21 a3 jsr SB1 ;Outchar before stripping 25a8 80 30 suba #$30 ; 25aa 16 24 bd jsr shift_a 25ad 16 21 29 jsr get_time_char 25b0 81 30 cmpa #$30 25b2 18 25 ff 26 lblo GET_DATE 25b6 81 39 cmpa #$39 25b8 18 22 ff 20 lbhi GET_DATE 25bc 36 psha 25bd 84 0f anda #%00001111 25bf f6 08 00 ldab TEMP1 25c2 18 06 aba 25c4 81 01 cmpa #1 25c6 18 25 ff 12 lblo GET_DATE 25ca 81 12 cmpa #$12 25cc 18 22 ff 0c lbhi GET_DATE 25d0 7a 08 10 staa time_months 25d3 32 pula 25d4 16 21 a3 jsr SB1 ;Outchar before stripping 25d7 86 2f ldaa #'/' 25d9 16 21 a3 jsr SendByte ;get days 25dc 16 21 29 jsr get_time_char 25df 81 0d cmpa #CR ;check if cr 25e1 18 27 00 49 lbeq datex ;yes, go set date 25e5 81 30 cmpa #$30 25e7 18 25 fe f1 lblo GET_DATE 25eb 81 33 cmpa #$33 25ed 18 22 fe eb lbhi GET_DATE 25f1 16 21 a3 jsr SB1 ;Outchar before stripping 25f4 80 30 suba #$30 ; 25f6 16 24 bd jsr shift_a 25f9 16 21 29 jsr get_time_char 25fc 81 30 cmpa #$30 25fe 18 25 fe da lblo GET_DATE 2602 81 39 cmpa #$39 2604 18 22 fe d4 lbhi GET_DATE 2608 36 psha 2609 84 0f anda #%00001111 260b f6 08 00 ldab TEMP1 260e 18 06 aba 2610 81 01 cmpa #1 2612 18 25 fe c6 lblo GET_DATE 2616 81 31 cmpa #$31 2618 18 22 fe c0 lbhi GET_DATE 261c 7a 08 0f staa time_days 261f b6 08 11 ldaa leap_var 2622 f6 08 0f ldab time_days 2625 18 06 aba 2627 7a 08 0f staa time_days 262a 32 pula 262b 16 21 a3 jsr SB1 ;Outchar before stripping datex 262e b6 08 11 ldaa leap_var 2631 ce 10 02 ldx #leap_year 2634 6a 00 staa 0,x 2636 18 20 fd 1d lbra NEW_DATE_INIT date_ex 263a 79 08 09 clr time_flag 263d 79 08 0a clr date_flag 2640 3d rts ;----------------------------------------------------------------------------- READ_TIME_SEC 2641 18 0b 02 08 06 movb #seconds_reg_address,rtc_reg_address ;slave control register 2646 16 26 f3 jsr READ_TIME 2649 18 0c 08 0b 08 0c movb time_temp,time_seconds 264f 16 27 b8 jsr stop_condition 2652 3d rts READ_TIME_MIN 2653 18 0b 03 08 06 movb #minutes_reg_address,rtc_reg_address ;slave control register 2658 16 26 f3 jsr READ_TIME 265b 18 0c 08 0b 08 0d movb time_temp,time_minutes 2661 16 27 b8 jsr stop_condition 2664 3d rts READ_TIME_HR 2665 18 0b 04 08 06 movb #hours_reg_address,rtc_reg_address ;slave control register 266a 16 26 f3 jsr READ_TIME 266d 18 0c 08 0b 08 0e movb time_temp,time_hours 2673 16 27 b8 jsr stop_condition 2676 3d rts READ_TIME_DATE 2677 18 0b a2 08 05 movb #rtc_write_address,spi_write ;slave address 267c 18 0b 00 08 06 movb #rtc_control_reg_address,rtc_reg_address ;slave control register 2681 16 27 39 jsr WRITE_MOD ;status 2684 c6 08 ldab #8 2686 86 0b ldaa #status3 ;dump status data into rtc 2688 16 27 78 jsr clock_bits 268b 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc 268e a7 nop 268f a7 nop 2690 a7 nop 2691 a7 nop 2692 16 27 b8 jsr stop_condition 2695 18 0b 05 08 06 movb #year_date_reg_address,rtc_reg_address ;slave control register 269a 07 57 bsr READ_TIME 269c 18 0c 08 0b 08 0f movb time_temp,time_days 26a2 16 27 b8 jsr stop_condition 26a5 3d rts READ_TIME_WEEK 26a6 18 0b 06 08 06 movb #week_month_reg_address,rtc_reg_address ;slave control register 26ab 07 46 bsr READ_TIME 26ad 18 0c 08 0b 08 0e movb time_temp,time_hours 26b3 16 27 b8 jsr stop_condition 26b6 3d rts READ_TIME_MNTH 26b7 18 0b a2 08 05 movb #rtc_write_address,spi_write ;slave address 26bc 18 0b 00 08 06 movb #rtc_control_reg_address,rtc_reg_address ;slave control register 26c1 16 27 39 jsr WRITE_MOD ;status 26c4 c6 08 ldab #8 26c6 86 0b ldaa #status3 ;dump status data into rtc 26c8 16 27 78 jsr clock_bits 26cb 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc 26ce 16 27 b8 jsr stop_condition 26d1 18 0b 06 08 06 movb #week_month_reg_address,rtc_reg_address ;slave control register 26d6 07 1b bsr READ_TIME 26d8 18 0c 08 0b 08 10 movb time_temp,time_months 26de 16 27 b8 jsr stop_condition 26e1 3d rts READ_TIME_YR 26e2 18 0b 05 08 06 movb #year_date_reg_address,rtc_reg_address ;slave control register 26e7 07 0a bsr READ_TIME 26e9 18 0c 08 0b 10 00 movb time_temp,time_years 26ef 16 27 b8 jsr stop_condition 26f2 3d rts READ_TIME ; ;set slave address and word address 26f3 79 08 07 clr read_write_flag 26f6 18 0b a2 08 05 movb #rtc_write_address,spi_write ;slave address 26fb 16 27 39 jsr WRITE_MOD 26fe 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc 2701 18 0b 01 08 07 movb #1,read_write_flag 2706 18 0b a3 08 04 movb #rtc_read_address,spi_read 270b 16 27 5d jsr READ_CMD 270e 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc 2711 79 08 0b clr time_temp 2714 c6 08 ldab #8 2716 07 04 bsr SHIFT_BITS 2718 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc 271b 3d rts ;----------------------------------------------------------------------------- SHIFT_BITS 271c 4c 56 40 bset PORTP,SCL ;Get data from RTC 271f 16 27 fd jsr small_delay 2722 96 56 ldaa PORTP ;read bit in 2724 16 27 fd jsr small_delay 2727 4d 56 40 bclr PORTP,SCL 272a 16 27 fd jsr small_delay 272d 84 80 anda #SDA ;mask unwanted bits 272f 10 fe clc ;clear carry 2731 48 asla ;Shift content to carry 2732 75 08 0b rol time_temp ;store bit into mem 2735 53 decb ;decrement counter 2736 26 e4 bne SHIFT_BITS o 2738 3d rts cond buff ;---------------------------------------- WRITE_MOD 2739 16 27 fd jsr small_delay ;do some delay 273c 4c 56 c0 bset PORTP,%11000000 ;make sure both SDA and SCL are high 273f 4c 57 c0 bset DDRP,%11000000 ;make sure bit 6, and 7 are output 2742 16 27 fd jsr small_delay ;do some delay 2745 16 27 ab jsr start_condition 2748 79 08 07 clr read_write_flag 274b 16 27 73 jsr WRITE_CMD ;go start sequence 274e 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc 2751 c6 08 ldab #8 2753 b6 08 06 ldaa rtc_reg_address ;word address 0 2756 16 27 78 jsr clock_bits 2759 16 27 c8 jsr acknowledge ;get acknowledge signal from rtc 275c 3d rts ;---------------------------------------- READ_CMD 275d 16 27 fd jsr small_delay ;do some delay 2760 4c 56 c0 bset PORTP,%11000000 ;make sure both SDA and SCL are high 2763 4c 57 c0 bset DDRP,%11000000 ;make sure bit 6, and 7 are output 2766 16 27 fd jsr small_delay ;do some delay 2769 16 27 ab jsr start_condition 276c c6 08 ldab #8 276e b6 08 04 ldaa spi_read ;get rtc address 2771 20 05 bra clock_bits ;---------------------------------------- WRITE_CMD 2773 c6 08 ldab #8 2775 b6 08 05 ldaa spi_write ;get rtc address clock_bits 2778 10 fe clc ;clear carry bit 277a 48 asla ;move high bit into carry 277b 25 02 bcs clock_bit_high ;clock a high bit if carry is set 277d 20 16 bra clock_bit_low ;clock a low bit if carry is not set clock_bit_high 277f 4c 56 80 bset PORTP,SDA ;set SDA hi 2782 16 27 fd jsr small_delay 2785 4c 56 40 bset PORTP,SCL ;strobe SDA 2788 16 27 fd jsr small_delay 278b 4d 56 40 bclr PORTP,SCL 278e 16 27 fd jsr small_delay 2791 53 decb ;decrement counter 2792 26 e4 bne clock_bits o 2794 3d rts clock_bit_low 2795 4d 56 80 bclr PORTP,SDA ;set SDA lo 2798 16 27 fd jsr small_delay 279b 4c 56 40 bset PORTP,SCL ;strobe SDA 279e 16 27 fd jsr small_delay 27a1 4d 56 40 bclr PORTP,SCL 27a4 16 27 fd jsr small_delay 27a7 53 decb ;decrement counter 27a8 26 ce bne clock_bits o 27aa 3d rts start_condition 27ab 4d 56 80 bclr PORTP,SDA ;set SDA low to start process 27ae 16 27 fd jsr small_delay 27b1 4d 56 40 bclr PORTP,SCL ;set SCL low to satisfy start process 27b4 16 27 fd jsr small_delay 27b7 3d rts stop_condition ; bclr PORTP,SDA ;set SDA lo 27b8 16 27 fd jsr small_delay ;do some delay 27bb 4c 56 40 bset PORTP,SCL ;set SCL lo 27be 16 27 fd jsr small_delay ;do some delay 27c1 4c 56 80 bset PORTP,SDA ;set SDA hi 27c4 16 27 fd jsr small_delay 27c7 3d rts acknowledge 27c8 4d 57 80 bclr DDRP,SDA ;make SDA (bit 7 of PORTC) as input 27cb 16 27 fd jsr small_delay ; ldab PORTP ; nop ; nop 27ce 4c 56 40 bset PORTP,SCL 27d1 16 27 fd jsr small_delay 27d4 d6 56 ldab PORTP 27d6 4d 56 40 bclr PORTP,SCL 27d9 16 27 fd jsr small_delay 27dc c4 80 andb #SDA ;clear unwanted bits 27de 10 fe clc ;clear carry bit before shifting 27e0 58 aslb ;Shift content to carry 27e1 24 04 bcc yes_acknowledge ;check if carry is set no_acknowledge ;carry is not set. No acknowledge 27e3 79 08 08 clr g 27e6 3d rts yes_acknowledge ;carry is set. There is acknowledge 27e7 72 08 08 inc ack_flag ;set acknowledge flag 27ea b6 08 07 ldaa read_write_flag 27ed 27 01 beq writing 27ef 3d rts writing ;ready to send stop condition 27f0 4d 56 80 bclr PORTP,SDA ;set SDA lo 27f3 4c 57 80 bset DDRP,SDA ;make SDA (bit 7 of PORTP) as output 27f6 3d rts ;----------------------------------------------------------------------------- delay 27f7 35 pshy 27f8 cd 00 00 ldy #0 27fb 20 04 bra dly small_delay 27fd 35 pshy 27fe cd 00 0a ldy #10 dly 2801 04 36 fd dbne y,dly 2804 31 puly 2805 3d rts ;------------------------------------------------------------------------------ ;4 digit bcd to 16 bit hex conversion 2806 00 01 digit_1 fdb 1 2808 00 0a digit_10 fdb 10 280a 00 64 digit_100 fdb 100 280c 03 e8 digit_1000 fdb 1000 bcd_to_hex 280e 18 03 00 00 08 17 movw #0,result ;initialize variables 2814 18 03 00 00 08 19 movw #0,result+2 281a 18 03 00 00 08 00 movw #0,TEMP1 2820 f6 10 00 ldab time_years 2823 07 38 bsr shift_b 2825 ce 28 0c ldx #digit_1000 2828 cd 08 00 ldy #TEMP1 282b 18 12 08 17 emacs result 282f f6 10 00 ldab time_years 2832 07 2d bsr shift_bb 2834 ce 28 0a ldx #digit_100 2837 cd 08 00 ldy #TEMP1 283a 18 12 08 17 emacs result 283e f6 10 01 ldab time_years+1 2841 07 1a bsr shift_b 2843 ce 28 08 ldx #digit_10 2846 cd 08 00 ldy #TEMP1 2849 18 12 08 17 emacs result 284d f6 10 01 ldab time_years+1 2850 07 0f bsr shift_bb 2852 fd 08 19 ldy result+2 2855 19 ed aby 2857 b7 c6 xgdy 2859 7c 08 00 std TEMP1 285c 3d rts shift_b 285d 54 lsrb ;Shift content 4 times 285e 54 lsrb 285f 54 lsrb 2860 54 lsrb shift_bb 2861 c4 0f andb #%00001111 2863 87 clra 2864 7c 08 00 std TEMP1 2867 3d rts ;----------------------------------------------------------------------------- ;HTOD-SUBROUTINE TO CONVERT A 16-BIT HEX NUMBER TO A 5 DIGIT DECIMAL ; HTOD 2868 ec 00 LDD 0,X ;D=HEX VALUE TO BE CONVERTED 286a ce 27 10 LDX #10000 286d 18 10 IDIV ;FREQ+10,000 ->X; REMAINDER->D 286f b7 c5 XGDX 2871 cb 30 ADDB #$30 2873 7b 08 12 STAB DBUFR 2876 b7 c5 XGDX 2878 ce 03 e8 LDX #1000 287b 18 10 IDIV 287d b7 c5 XGDX 287f cb 30 ADDB #$30 2881 7b 08 13 STAB DBUFR+1 2884 b7 c5 XGDX 2886 ce 00 64 LDX #100 2889 18 10 IDIV 288b b7 c5 XGDX 288d cb 30 ADDB #$30 288f 7b 08 14 STAB DBUFR+2 2892 b7 c5 XGDX 2894 ce 00 0a LDX #10 2897 18 10 IDIV 2899 cb 30 ADDB #$30 289b 7b 08 16 STAB DBUFR+4 289e b7 c5 XGDX 28a0 cb 30 ADDB #$30 28a2 7b 08 15 STAB DBUFR+3 P5DEC 28a5 ce 08 12 LDX #DBUFR ;POINT AT DECIMAL 28a8 86 30 LDAA #$30 ;CHECK FOR LEADING ZEROS 28aa a1 00 CMPA 0,X ;CHECK FOR 10,000S DIGIT 28ac 26 19 BNE P10K ;START AT 10K DIGIT 28ae 07 3d BSR SKP1 ;INX AND PRINT A SPACE 28b0 a1 00 CMPA 0,X ;CHECK FOR 1,000S 28b2 26 1b BNE P1K ;START AT 1K DIGIT 28b4 07 37 BSR SKP1 28b6 07 35 BSR SKP1 28b8 09 DEX 28b9 a1 00 CMPA 0,X ;CHECK FOR 100S DIGIT 28bb 26 1a BNE P100 ;START AT 100 DIGIT 28bd 07 2e BSR SKP1 28bf a1 00 CMPA 0,X ;CHECK 10S DIGIT 28c1 26 1c BNE P10 28c3 07 28 BSR SKP1 28c5 20 20 BRA P1 ;START AT 1S DIGIT 28c7 a6 00 P10K LDAA 0,X ;10,000 DIGIT 28c9 34 PSHX 28ca 16 21 a3 jsr SB1 28cd 30 PULX 28ce 08 INX 28cf a6 00 P1K LDAA 0,X 28d1 34 PSHX 28d2 16 21 a3 jsr SB1 28d5 30 PULX 28d6 08 INX 28d7 a6 00 P100 LDAA 0,X 28d9 34 PSHX 28da 16 21 a3 jsr SB1 28dd 30 PULX 28de 08 INX 28df a6 00 P10 LDAA 0,X 28e1 34 PSHX 28e2 16 21 a3 jsr SB1 28e5 30 PULX 28e6 08 INX 28e7 a6 00 P1 LDAA 0,X 28e9 16 21 a3 jsr SB1 28ec 3d RTS 28ed 36 SKP1 PSHA 28ee 08 INX 28ef 86 20 LDAA #$20 28f1 16 21 a3 jsr SB1 28f4 32 PULA 28f5 3d RTS #include spi_ee.ASM ;spi_ee.asm ******************************************************************************* *REVISION HISTORY: * *DATE REV. NO. DESCRIPTION * *March 16, 2000 1.00 Spi eeprom *Author: Exequiel Rarama ******************************************************************************* ; ;setup PORTS for SPI ; ; init_spi 28f6 18 0b e0 00 d7 movb #spi_mask2,DDRS 28fb 18 0b e0 00 d6 movb #spi_mask2,PORTS 2900 18 0b 04 00 db movb #%100,PURDS ; movb #spi_mask3,SP0CR1 ;SPE=1, MSTR=1, CPOL,CPHA=0, SWOM=1 2905 18 0b 50 00 d0 movb #spi_mask1,SP0CR1 ;SPE=1, MSTR=1, CPOL,CPHA,SWOM=0 290a 18 0b 08 00 d1 movb #8,SP0CR2 ; bclr SP0CR2,%01 ;SPC0=0, Normal mode 290f 18 0b 03 00 d2 movb #spi_baud4,SP0BR ;set clock to 1 Mhz 2914 96 d3 ldaa SP0SR ;clear flag and buffer 2916 96 d5 ldaa SP0DR 2918 18 03 00 10 08 1d movw #us8,u_delay_var 291e 4c 56 10 bset PORTP,slave_select ;slave select for spi eeprom 2921 4c 57 10 bset DDRP,slave_select ;slave select for spi eeprom 2924 16 27 fd jsr small_delay 2927 4d 56 10 bclr PORTP,slave_select ;enable cs 292a 86 06 ldaa #%110 ;set WREN 292c 16 2a 33 jsr dump_spi_data 292f 4c 56 10 bset PORTP,slave_select ;disable cs 2932 79 08 25 clr ee_rd_wr_flag 2935 3d rts ;----------------------------------------------------------------------------- go_read ;get address to read 2936 16 21 16 jsr GetChar 2939 16 21 a3 jsr SendByte ;echo the character 293c f6 08 23 ldab sci_flag ;check for character 293f 27 2d beq go_read10 2941 79 08 23 clr sci_flag ;check for character 2944 16 21 49 jsr Hex2Bin ;convert char to hex 2947 36 psha ;store temp. 2948 fc 08 21 ldd eeprom_address ;get data and shift 4 times 294b 59 lsld 294c 59 lsld 294d 59 lsld 294e 59 lsld 294f b7 c5 xgdx ;exchange d to x 2951 33 pulb ;get save date 2952 1a e5 abx ;add to eeprom_address data 2954 7e 08 21 stx eeprom_address ; and save it 2957 73 08 24 dec char_counter 295a 26 12 bne go_read10 295c 79 08 25 clr ee_rd_wr_flag 295f 16 21 aa jsr PutNewLine 2962 16 29 fc jsr read_spi 2965 16 21 aa jsr PutNewLine 2968 ce 20 3f ldx #wait_here ;go back to wait loop 296b 7e 08 26 stx states go_read10 296e 3d rts ;----------------------------------------------------------------------------- go_write ;get address to write to and data to save 296f 16 21 16 jsr GetChar 2972 16 21 a3 jsr SendByte ;echo the character 2975 f6 08 23 ldab sci_flag ;check for character 2978 27 53 beq go_write20 297a 79 08 23 clr sci_flag ;check for character 297d 16 21 49 jsr Hex2Bin ;convert char to hex 2980 36 psha ;store temp. 2981 b6 08 24 ldaa char_counter 2984 81 02 cmpa #2 2986 23 14 bls go_write10 2988 fc 08 21 ldd eeprom_address ;get data and shift 4 times 298b 59 lsld 298c 59 lsld 298d 59 lsld 298e 59 lsld 298f b7 c5 xgdx ;exchange 2991 33 pulb ;get save date 2992 1a e5 abx ;add to eeprom_address data 2994 7e 08 21 stx eeprom_address ; and save it 2997 73 08 24 dec char_counter 299a 26 31 bne go_write20 go_write10 299c b6 08 24 ldaa char_counter 299f 81 02 cmpa #2 29a1 27 0b beq shift10 29a3 33 pulb 29a4 b6 08 20 ldaa eeprom_data 29a7 18 06 aba 29a9 7a 08 20 staa eeprom_data 29ac 20 0d bra shift20 shift10 29ae 32 pula 29af 48 lsla 29b0 48 lsla 29b1 48 lsla 29b2 48 lsla 29b3 7a 08 20 staa eeprom_data 29b6 73 08 24 dec char_counter 29b9 20 12 bra go_write20 shift20 29bb 79 08 25 clr ee_rd_wr_flag 29be 16 21 aa jsr PutNewLine 29c1 16 29 ce jsr write_spi 29c4 16 21 aa jsr PutNewLine 29c7 ce 20 3f ldx #wait_here ;go back to wait loop 29ca 7e 08 26 stx states go_write20 29cd 3d rts ;----------------------------------------------------------------------------- write_spi 29ce 4d 56 10 bclr PORTP,slave_select ;enable cs 29d1 86 06 ldaa #%110 ;set WREN (make sure to enable write) 29d3 16 2a 33 jsr dump_spi_data 29d6 a7 nop 29d7 a7 nop 29d8 4c 56 10 bset PORTP,slave_select ;disable cs 29db 16 27 fd jsr small_delay 29de 4d 56 10 bclr PORTP,slave_select ;enable cs 29e1 86 02 ldaa #%010 ;write to data array 29e3 16 2a 33 jsr dump_spi_data 29e6 b6 08 21 ldaa eeprom_address ;dump msb address 29e9 16 2a 33 jsr dump_spi_data 29ec b6 08 22 ldaa eeprom_address+1 ;dump lsb address 29ef 16 2a 33 jsr dump_spi_data 29f2 b6 08 20 ldaa eeprom_data ;write data to eeprom 29f5 16 2a 33 jsr dump_spi_data 29f8 4c 56 10 bset PORTP,slave_select ;disable cs 29fb 3d rts ;----------------------------------------------------------------------------- read_spi 29fc 4d 56 10 bclr PORTP,slave_select ;enable cs 29ff 86 03 ldaa #%011 ;read data array 2a01 16 2a 33 jsr dump_spi_data 2a04 b6 08 21 ldaa eeprom_address ;dump msb address 2a07 16 2a 33 jsr dump_spi_data 2a0a b6 08 22 ldaa eeprom_address+1 ;dump lsb address 2a0d 16 2a 33 jsr dump_spi_data 2a10 86 00 ldaa #0 ;dummy write to get data from eeprom 2a12 16 2a 33 jsr dump_spi_data 2a15 4c 56 10 bset PORTP,slave_select ;disable cs 2a18 37 pshb 2a19 32 pula 2a1a 16 21 78 jsr SendASCIIHex 2a1d 3d rts ;----------------------------------------------------------------------------- us_delay 2a1e 4d 86 80 bclr TSCR,TEN ;stop the timer so we can produce accurate time ;delays 2a21 fc 08 1d ldd u_delay_var ;get constant for 2us delay 2a24 d3 84 addd TCNT 2a26 5c 90 std TC0 2a28 4c 86 80 bset TSCR,TEN ;turn on the timer 2a2b 4f 8e 01 fc brclr TFLG1,$01,* ;wait here for 8us 2a2f 4d 86 80 bclr TSCR,TEN ;turn off the timer 2a32 3d rts dump_spi_data 2a33 d6 d3 ldab SP0SR ;clear flag and buffer 2a35 d6 d5 ldab SP0DR 2a37 79 08 1f clr spi_int_flag ;clear for next spi dump 2a3a 4c d0 80 bset SP0CR1,SPIE ;Enable spi interrupt 2a3d 5a d5 staa SP0DR ;dump to spi to start playback 2a3f 1f 08 1f 01 fb brclr spi_int_flag,$01,* ;wait here for spi int 2a44 4d d0 80 bclr SP0CR1,SPIE ;Disable spi interrutp 2a47 d6 d3 ldab SP0SR ;clear flag and buffer 2a49 d6 d5 ldab SP0DR 2a4b 79 08 1f clr spi_int_flag ;clear for next spi dump 2a4e 3d rts spi_int 2a4f 1c 08 1f 01 bset spi_int_flag,%00000001 2a53 96 d3 ldaa SP0SR 2a55 96 d5 ldaa SP0DR 2a57 0b rti ffd8 org $FFD8 ffd8 2a 4f FDB spi_int ;SPI SERIAL TRANSFER COMPLETE Total errors: 0 Total warnings: 0